In earlier days, the primary means for storing data in computer, microprocessor and similar systems, resided in a transistor-based high speed circuit that stored each bit of information--a so-called static random access memory device, termed SRAM, summarily described, for example, on page 295-300 of a catalog of Samsung Electronics entitled MOS Memory, 1993/94. A Samsung Type KM644002 cmos SRAM, for example, was presented in a 32-pin plastic unit (400 mil) providing 1,048,576 words by 4 bits and using four common input and output lines and an output enable pin operating faster than the address access time at read cycle--the fast access times ranging from 15 to 25 ns. In order uniquely to select one of the over 1 million locations, 20 address bits are rejoined (20 of the pins being address pins) along with 4 data pins and control signals.
In an effort to meet increased RAM requirements, the concept was evolved of storing each bit in a small capacitor on the silicon unit or die, the integration of a large number of capacitors taking far less space than transistors--so-called dynamic random access memory or DRAM units. The resulting advantages of the DRAM unit in increased storage capacity, higher data bandwidth and savings in terms of device size, board space, power consumption and cost, particularly when large numbers of such devices are implemented in a design, outweighed the necessity for periodic charging of capacitors, and more complex access mechanisms and control circuits; and DRAM became one of the most, if not the most, popular type of memory.
The external circuit interface of the DRAM, moreover, differs significantly from the SRAM. Contrasting the illustrative Samsung Type KM644002 SRAM above-described, with a corresponding Samsung Type KM44C1000B CMOS DRAM, as described on pages 330-337 of said Samsung catalog, the addressing is similar to uniquely identifying an element within a matrix, with each location in the address space being accessed by providing a row address and a column address. For the 1 million.times.4 bit example, only a total of 20 address bits are required, 10 bits used to select the row in which the bit is located and 10 bits selecting the column of the desired bit in the selected row. As compared with the SRAM device only 10 address pins are provided and 4 data bits along with few control lines, resulting in a package of just 20 pins, providing considerable savings in terms of board space, power consumption and cost. The DRAM access mechanism is as follows. A 10 bit row address followed by a 10 bit column address are provided on the same pins sequentially by the external circuit, with the internal circuit using this sequentially provided information to select the desired unique location as described in the said catalog. The external circuit interface of this DRAM is asynchronous in nature and thus it is also called an asynchronous or async DRAM.
This sequential occurrence of row and column addresses instead of presenting the entire address at the same time, however, delays the storage and retrieval of information compared to the SRAM, and as more particularly shown on said pages 336 and 337, for example, as compared with the SRAM read and write access cycles described on pages 299 and 300.
Over a period of time, however, system requirements expanded, dictating capacity, higher data bandwidth, faster access time, burst mode accesses, and synchronous operation as distinguished from async DRAM.
The art progressed with incremental improvements, successively providing higher density async DRAMs with faster access time and limited burst mode capability, such as page mode access. DRAMs with synchronous interface then also came into existence. Higher data bandwidth devices with larger pin count were also developed, but had limited market success due to their large package size. The higher data bandwidth requirement, moreover, had to be fulfilled by using either more components or wider data bandwidth components with larger pin counts, unfortunately but necessarily leading to more board space and power consumption and the disadvantages thereof.
Such development in this art leading incrementally to these enhanced devices providing higher density and faster speed, however, still stayed with the basic architecture, external circuit interface and access mechanism. Each new generation of DRAM had higher storage capacity and generally faster access time as they moved from 32K to 64K, 256K, 1M, 4M, 16M and 64M with 256M under development.
This async DRAM evolution was largely fueled by the availability of new generations of high speed microprocessors with large data bandwidth and addressing capabilities. These new processors offered data transfer modes where multiple memory accesses are made in a burst to speed up the storage and retrieval process. Since the async DRAMs, however, have limited burst mode capability, they created bottlenecks in the system perfomance as burst transfers became a significant portion of all the accesses to memories. The requirement to process the burst mode efficiently and development of new generation of CAD tools and design methodologies thus demanded synchronous designs and gave impetus to developing the before-mentioned synchronous or sync DRAM (SDRAM). A major departure was made when moving from async to sync DRAM.
A clock is provided in the SDRAM and all accesses are synchronous to the clock. It is optimized for burst transfer accesses and has substantially higher burst access speeds. After initial set up time, data is stored or retrieved every clock cycle for the whole burst. A typical 4M.times.4 SDRAM and its internal structure is the micron type MT48 described on pages 2-1 and 2-2 of the Micron Semiconductor data book of 1994. The access mechanism for read and write cycles of SDRAM devices is described, for example, on pages 4-525 and 4-526 of the Texas Instruments catalog entitled MOS Memory, 1993, with such SDRAM having different access mechanisms than async DRAM and requiring different external circuits to generate the control signals.
It should be noted, however, that mind-set of those skilled in this art required that both synchronous and async DRAMs should retain the notion of sequentially providing row and column accessed addresses, and with the data interface implemented separately from the address interface.
While major demands created by the growth, in the system arena were thus solved between async and SDRAMs, one problem has remained largely unsolved; namely, the growth in data bandwidth has deleteriously consumed large numbers of DRAMs occupying precious board space and demanding more power.
In the current state of the art, thus, a typical configuration employs multiple DRAMs to provide wider bandwidth and large memory arrays. This is better illustrated with an example.
Assuming a processor with a 64-bit wide data bus and system requirements of 4M.times.64 memory, the use of both SDRAM and async DRAMs, requires 16 DRAMs, assuming 4M.times.4 DRAM as a basic unit. If, on the other hand, 4M.times.16 DRAMs are used (much larger package size than 4M.times.4) then only 4 DRAMs are needed, but they still occupy substantially more space than four 4M.times.4 packages.
It is therefore obvious that in spite of major changes made while developing SDRAM, the number of components for similar configuration has stayed the same. This continues to put huge demand on the board space as the memory requirement grows. In fact, the SDRAMs have larger package sizes for comparable densities, with 16 DRAMs occupying more space than 16 async DRAMs.
Granularity is another problem or issue with the existing DRAMs. There is no easy way to get odd sizes (sizes which are not multiples of 4) such as 2M.times.64 or 6M.times.64, without using large numbers of components. As an example, if it is desired to get a 6M.times.64 memory configuration, then thirty two 4M.times.4 devices are required.
Pin-to-pin compatibility with successive generation, moreover, exists only for a very narrow range. The package size grows quickly along with the density of the DRAM; and this forces redesigns to keep up with ever-increasing system memory requirements, since higher density chips require bigger footprints.
In general, with higher numbers of components of smaller package size or smaller numbers of components with larger package size, the current state of the art of DRAM technology consistently demands increased board space higher power consumption, more manufacturing and assembly cost, lower MTBF, coarse granularity, and pin compatibility only for a very small range of DRAMs. These problems still persists in spite of two decades of work.
The startling discovery underlying the present invention, synergistically breaks through all these disadvantages and limitations enabling, for the same configuration, a reduced number of components; and, for comparable density, providing smaller package sizes with lower power consumption, lesser manufacturing and assembly costs, better MTBF, finer granularity, and greatly expanded pin compatibility for a wide range of DRAMs. The invention, indeed, provides increased capability in data bandwidth and addressing range over current DRAM devices (using the same pin count and size device) or equivalent bandwidth and addressing range with smaller DRAM devices packages, both async and SDRAM. This is accomplished with a total departure from the direction uniformly taken in this art over the past decades, employing, rather, a novel interface and associated access mechanisms and procedure.